1. Field of the Invention
The present invention relates to a peripheral unit selection system constructed by connecting peripheral units to a CPU unit via a signal line such as a computer system or a programmable controller, in which the CPU unit selectively accesses the peripheral units.
2. Description of the Prior Art
Generally in a computer system or a programmable controller, the system is constructed by combining a CPU unit having a processor that operates according to a program with a peripheral unit having a function of assisting the CPU unit for the operations of data input/output and complicated calculation. It is usual to provide a plurality of peripheral units, and as shown in FIG. 23, peripheral units 1 are connected to a CPU unit 2 via a signal bus line 3. To communicate between CPU unit 2 and individual peripheral unit 1, it is necessary to individually select the peripheral units 1. In order to satisfy this demand, there has been considered the following structures.
A signal line for selecting each peripheral unit 1 is provided between the CPU unit 2 and each peripheral unit 1 so as to select each peripheral unit 1 via each signal line aside from the signal line 3 for communicating data. However, this structure requires signal lines corresponding in number to the peripheral units 1, causing a problem that the number of wiring lines increases according to the increase in number of the peripheral units 1 with the increase of the system scale.
In contrast to the above, there has been a structure in which each peripheral unit 1 is preparatorily provided with an individual unit address, and by sending a call address from the CPU unit 2 to the signal line 3, the peripheral unit 1 in which the unit address coinciding with the call address is set is selected. According to this structure, the peripheral units 1 are time-sharingly selected, and this arrangement has the advantage that the number of wiring lines does not increase even when there is an increased number of peripheral units 1 with the increase of the system scale.
However, according to the prior art structures, the unit address of each peripheral unit 1 has been set by a switch, and therefore, the unit address setting work is troublesome. Furthermore, the unit addresses have been individually set in the peripheral units 1. Therefore, in the case where an increased number of peripheral units 1 are there or an additional peripheral unit 1 is subsequently incorporated, there is the problem that erroneous setting such as overlapped unit address setting tends to occur.
In the international application published Jul. 11, 1996 (WO 96/21181) based on U.S. application Ser. No. 08/365,655 filed Dec. 29, 1994, there is disclosed an expansion module address method and apparatus wherein a programmable controller (PLC) base unit sends an address number to an expansion I/O module and to modules attached thereto, each expansion module takes the number it receives and considers it to be own address number, and the expansion module decrements the number and passes it onto the next module unless the number is zero. This method and apparatus may be a solution to the problem mentioned above.